Résumé

 

Personal information

Name
Américo Dias
Age
42 years old
Marital Status
Married
Current position
Sr. Analog ASIC Designer
Location
Porto, Portugal
Languages
Portuguese, English, Spanish
Interests
Technology, Photography

Experience

Nov 2018 – Present
Sr. Analog ASIC Designer

Knowles Corporation

Design and layout of analog blocks for performance audio group.

Nov 2017 – Jul 2018
3 mos
Full-Custom IC Layout Engineer (Contractor)

Adesto Technologies

Full-custom layout of analog blocks.

Accomplishments:

    • Completed the layout of 3 medium size analog blocks: Two auxiliary blocks containing amplifiers, level shifters, and bias circuitry, among other functionalities in TSMC 40nm and a 100MHz RC Clock Generator in TSMC 55nm.

Tools and Technologies:

    • Schematic capture with Cadence Virtuoso IC6.
    • Physical verification and parasitic extraction with Mentor Graphics Calibre.
    • Version Control with SVN.
    • TSMC 55 and 40nm.
Nov 2017 – Jul 2018
9 mos
Sr. Analog IC Design Engineer

Sigma Designs / Silicon Labs

As part of the ASIC design team, my main responsibilities are to create specifications, supervise and design analog blocks for Z-Wave integrated circuits.

Accomplishments:

    • Design of an 120mA LDO using a replica-regulator topology to achieve a very high power supply rejection ratio (PSRR) for a sub-GHz PA in 40nm TSMC process.
    • Discovered the root cause of an issue affecting a 40 MHz crystal oscillator. This issue was previously investigated by staff engineers and engineers from the crystal supplier without reaching any conclusion. This work required hands-on work in the laboratory to obtain measurement results and PEX simulations to correlate with these results.
    • Development of a Delta-Sigma modulator model in SystemC-AMS. Comparing with Cadence Spectre macro-model, the SystemC-AMS version was 100x faster to simulate with the same precision.
    • One of my works with SystemC-AMS was highlighted by Coseda Technologies on their website (https://www.coseda-tech.com/links).

Tools and Technologies:

    • Schematic capture with Synopsys Laker and Cadence Virtuoso IC6.
    • Physical verification and parasitic extraction with Mentor Graphics Calibre.
    • Simulation with Cadence Spectre and Mentor Graphics Eldo.
    • Modeling with Spice/Verilog-A and SystemC-AMS.
    • Scripting with Python, Cadence Skill/Ocean and tcsh.
    • Version Control with ClioSoft SOS, Perforce and git.
    • TSMC 55 and 40nm.
Apr 2016 – Oct 2017
1 yr 7 mos
Senior Analog Design Engineer

Roxar Flow Measurement (Emerson Automation Solutions)

Reporting to the Downhole Product Development Manager, I was responsible for electromagnetic modelling as part of feasibility studies into new products. This has involved modelling the electromagnetic propagation and verifying models with laboratory measurements. I was involved in developing analog circuits for fault detection along transmission lines (Time-domain Reflectometer) and troubleshooting investigations on existing product lines.

Accomplishments:

    • Modeling of a low frequency wireless communication channel in spice using finite element method to estimate the mutual impedance and core loses. Before this work, the functionality of new designs had to be tested in practice, building very expensive prototypes in Stainless Steel 316 or even Inconel 625.
    • Modeling and linearization of a DC-DC converter using PWM-switch modelling. This work was crucial for stability analysis of a DC-DC power supply that was under development. This power supply had a high dynamic range of output voltages (12-360V) and currents (10-200mA), making it difficult to simulate due to the slow simulation time and the high number of operating modes to be simulated.

Tools and Technologies:

    • Schematic capture and PCB layout with Altium Designer 17.
    • Simulation with Linear Technology LT-Spice XVII.
    • Modeling with Spice, Matlab and FEMM.
    • Scripting with Python and Lua.
    • Version Control with Git.
    • Board level (PCB).
Jan 2013 – Mar 2016
3 yr 3 mos
Analog IC Design Engineer

SiliconGate

Full-custom design of analog blocks for power management IPs such as LDOs and DC-DC converters. Main tasks and responsibilities:

    • Block level topology selection, hand analysis, and IC transistor level implementation.
    • Schematic generation and simulation on modern CAD tools (Cadence tool set).
    • Worst case identification, top level simulation using hspice, stability analysis and compensation, Monte Carlo analysis, and simulation data analysis.
    • Physical layout design, signal grounding and routing tradeoffs, area optimization.
    • Post layout parasitic extraction and simulation, verification of all IC level performance metrics.
    • Budget time, manage schedule and complete complex IC design tasks on time.
    • Account for limitations of system level specifications, testability, debug, characterization, production and yield targets in the IC design phase.
    • Prepare technical documents and reports about concluded projects.

Accomplishments:

    • Porting and redesign of several LDOs for different foundries and technology nodes.
    • Participation in the design of a new LDO family (SGC76) with differential feedback (ground-offset compensation).

Tools and Technologies:

    • Schematic capture with Cadence Virtuoso IC5 and IC6.
    • Physical verification and parasitic extraction with Mentor Graphics Calibre.
    • Simulation with Synopsys hspice.
    • Scripting with Python and Bash.
    • TSMC, UMC and SMIC in several nodes such as 90nm, 65nm, 45nm, 40nm and 28nm.
Jun 2011 – Dec 2012
1 yr 7 mos
Physical Design Engineer

Synopsys

As a Physical Design Engineer I was responsible for all phases of physical design of high performance PHYs from RTL to delivery of final GDSII. My responsibilities included: Create block floor-plan including pin placement, partitions and power grid. Develop and validate high performance low power clock network guidelines. Perform block level place and route and close the design to meet timing, area and power constraints. Generate and Implement ECOs to fix timing, noise and EM IR violations. Run Physical design verification flow at chip/block level and fix LVS/DRC violations.

Tools and Technologies:

    • Synthesis with Synopsys Design Compiler
    • Place & Route with Synopsys IC Compiler
    • Integration of analog blocks with Synopsys Custom Designer
    • Timing closure with Synopsys Primetime
    • Formal verification with Synopsys Formality
    • Electrical checks with Synopsys ICV, Synopsys Hercules and Mentor Graphics Calibre
    • Physical verification with Synopsys ICV, Synopsys Hercules and Mentor Graphics Calibre
    • TSMC, UMC and SMIC in several nodes down to 40nm.
Sep 2010 – Sep 2011
1 yr
Ph.D. Candidate

Faculdade de Engenharia da Universidade do Porto

Preparation for the Doctoral Programme in Electrical and Computer Engineering with focus on IC design. Concluded the first year with success with a score of 16 out of 20. I left the academy after this year but the Ph.D. remains a long-term objective.
I worked as adjunct professor responsible for practical classes.

Apr 2009 – Jul 2010
1 yr 4 mos
Researcher

INESC Porto

Development of an Attitude and Heading Reference System (AHRS) prototype for aerospace applications using microelectromechanical systems (MEMS) and mixed-signal microelectronics. I was responsible by developing the two main blocks of this system:

    • Analog: Analog frontend for a MEMS accelerometer. This frontend was based on a switched capacitor circuit and a chopper stabilized op-amp. It was designed in AMS 0.35um CMOS process.
    • Digital: Implementation of a Kalman filter to process data from the MEMS and a GPS system. This filter was implemented in a Xilinx Virtex 5 FPGA with a PowerPC CPU core running Linux. Several optimizations where required to allow real-time processing.

Accomplishments:

    • Both parts under my responsibility where developed and tested with very little guidance. I was able to develop the specifications, design the integrated circuit, send it to production – using IMEC service – and test the prototype.

Tools and Technologies:

    • FPGA development with Xilinx ISE Design Suite.
    • Schematic capture with Cadence Virtuoso IC5.
    • Physical verification and parasitic extraction with Mentor Graphics Calibre.
    • Simulation with Cadence Spectre.
    • Modeling with Matlab and Verilog-A.
    • Scripting with Cadence Skill/Ocean and Bash.
    • AMS 0.35um.
Sep 2008 – Apr 2009
8 mos
Firmware programmer

Tellus Mater, S.A.

Reporting to the hardware team leader, I was responsible for the firmware development for telemetry, telemedicine and security system.

May 2007 – Aug 2008
1 yr 4 mos
Country Sales Representative

Venco Electrónica S.A. and R.C. Microelectrónica S.A.

Reporting to the sales managers, in Spain, I was responsible by introducing these companies in the Portuguese market. My responsibilities ranged from managing the clients portfolio, product presentation, technical support, quotes, and definition of the paying conditions for all clients in Portugal.

Sep 2001 – Apr 2007
5 yr 8 mos
Hardware Technician

Corsisa Electrónica, Lda.

Development of hardware/firmware in optoelectronic and testing areas. Production technical support and quality control.

Education and Training

Sep 2010 – Aug 2011
(suspended)
Ph.D. Candidate, Electrical and Computer Engineering

Faculdade de Engenharia da Universidade do Porto

Upon completion of the master’s degree I entered the Doctoral Program in Electrical and Computer Engineering having concluded the first year with a score of 15 in 20. However, for a number of reasons, I decided to suspend my academic life to go back to work full-time.

During this year I worked as adjunct professor responsible for practical classes.

Sep 2000 – Aug 2010
M.Sc., Electrical and Computer Engineering, 14 out of 20

Faculdade de Engenharia da Universidade do Porto

The program was composed by two cycles of studies. The first cycle, had duration of three years and was equivalent to a bachelor’s degree. The second cycle lasted two more years. I specialized in telecommunications with a minor specialization in microelectronics and embedded systems. My master thesis consisted in the development of an ultra-wideband (UWB) transmitter for biomedical implants in 90nm CMOS process. The integrated circuit was produced and tested and I obtained a score of 19 in 20. For more details please visit this page.

Sep 1997 – Aug 2000
Technician, Electronics, 15 out of 20

Colégio de Gaia

During this course I learned the basic skills in the domain of telecommunications, digital and analogic electronics, microcontrollers, computed aided design, printed circuit boards, computer networks, etc.

After the completion of this course I was able to preform all the technical activities related to the installation, use, maintenance, adoption and repair of electronic and telecommunication equipment and systems, ensuring the optimization of its operation, in compliance with standards of health and safety and the specific regulations.

Honors and Awards

The work “Dual-Modulus Prescaler for the 2.4-GHz ISM Band” presented on the 2nd Meeting of Researchers of U. Porto (IJUP 2009) was selected as one of the five best works. The selected works were presented in São Paulo (Brazil) on the conferences SIICUSP’09 and CIC’09.
Fastest full custom layout designer of the year, EMEA region 2009, Cadence Design Systems, Inc.